>pic related - muh system resultwill we ever have system memory that will match in equal polarity to cache in terms of latency and bandwidth?
>>100164782>no L4 cache
>>100164782No. That's why cache is cache. It's faster but very expensive in various ways, so there's much less of it.
>he didn't buy up all the optane
>>100164836but what about 3d cache that amd made? couldn't we just slap 32gb of l3 or even l4 cache into the cpu? use that for system memory.
Babby's first memory wallEither ask IBM to resurrect OpenCAPI or stop crying
>>100164854>couldn't we just slap 32gb of l3 or even l4 cache into the cpu?Yes, if you want 0.1% yields and pay the cost of a yacht on a CPU
>>100164879so what you are saying is that it is actually possible?
>>100164885>so what you are saying is that it is actually possible?Understanding the difference between possible and feasible is a critical skill.
>>100164885As >>100164836 said, SRAM is fucking expensive, stacking only goes so far but nowhere near 32GB. Large amounts of cache will also increase die area and tank yields, which means fewer working chips from a wafer, therefore more expensive, so nobody would actually bother with that much cache for a bottom-of-the-barrel gayming CPU at least. Not to mention months and even years of tape-out, validation and so on and so forth
>>100164948Also assembling mistakes, if you decide to do it like AMD and solder the cache over a working die. If you fuck it up, you lose both a working chiplet and the cache, wonderful innit
>>100164967what about something like HBM?
>>100165086HBM has to be very close to the CPU/GPU, or else it negates the latency/nandwidth advantages. Then there's the interposer problem, which is very fragile, and HBM being dense means it traps a lot of heat, combining that with the usual thermal cycling makes it not last very much. Again, I don't think they would sell that to end-users again, AMD only did that with their GPUs because they couldn't compete in raw performance
>>100165166so system memory will always be a bottleneck then? we will never get stuff like 3d cache large enough that we won't need system memory?
My dream>on-package HBM like those new Xeons and rumoured Epycs as L4 cache>bring back 3D-Xpoint, improve it even further and use it as RAM, but big and persistent
>>100165620yeah i really don't get why we couldn't at least do HBM. i understand people say the interpose is delicate but i'm sure there can be some breakthroughs to make it more durable.the bandwidth and latency makes it well worth it.
>>100164854The larger the cache, the higher the latency. A 7800X3D already has ~3ns higher latency on its L3 cache than a 7700X, and that's just a 64MB increase. You could keep expanding the cache (assuming cost and die size are no object), but the latency will also keep going up. At some point you're severely compromising the point of CPU cache and making it not that much faster to access than system memory. The 128MB L4 cache on an i7-5775C has a latency of ~45ns, which is outright worse than a tuned memory setup on most modern Intel chips.
>>100167117what about something like HBM? can't believe we can never have something better than regular o' ram.
>>100167480HBM is complexity problem.
>>100164782>67nsholy shit that's slow, even for DDR5 standards.
>>100164825Damn, I really miss my old 5775C. That CPU was fun AF
